supertex inc. supertex inc. www.supertex.com hv6810 doc.# dsfp-hv6810 e070913 features ? high output voltage 80v ? high speed 5mhz @5.0v dd ? low power i bb 0.1ma (all high) ? active pull down 100a min @25 o c ? output source current 25ma @60v v bb ? each device drives 10 lines ? high-speed serially-shifted data input ? 5.0v cmos-compatible inputs ? latches on all driver outputs ? pin-compatible replacement for ucn5810a and tl4810a, tl4810b applications ? high speed dot matrix print head driver ? vfd (vacuum luorescent display) driver general descriptionthe hv6810 is a monolithic integrated circuit designed to drive a dot matrix or segmented vacuum luorescent display (vfd). these devices feature a serial data output to cascade additional devices for large displays. a 10-bit data word is serially loaded into the shift register on the positive-going transition of the clock. parallel data is transferred to the output buffers through a 10-bit d-type latch while the latch enable input is high, and is latched when the latch enable is low. when the blanking input is high, all of the outputs are low. outputs are structures formed by double-diffused mos (dmos) transistors with output voltage ratings of 80v and 25ma source-current capability. all inputs are compatible with cmos levels. 10-channel, serial-input latched display driver functional block diagram blanking latch enable q1 q9 q2 q10 1dc1 data input clock lc1 lc2 lc9 lc10 latches shift register ? ? ? 6 stages (q3 thru q8 not shown serial out c2 2d 1dc1 1d c1 1dc1 ? ? ? ? ? ? ? ? ? c2 2d c2 2d c2 2d ? ? ? v bb logic diagram (positive logic) downloaded from: http:///
2 hv6810 supertex inc. www.supertex.com doc.# dsfp-hv6810 e070913 recommended operating conditions sym parameter min typ max units conditions v dd supply voltage 4.5 - 5.5 v --- v bb high supply voltage 20 - 80 v --- v ss supply voltage - 0 - v --- v ih high-level input voltage (for v dd = 5.0v) 3.5 - 5.3 v --- v il low-level input voltage -0.3 - 0.8 v --- i oh continuous high-level q output current 25 - - ma --- f clk clock frequency - - 5.0 mhz --- t a operating ambient temperature -40 - +85 c --- absolute maximum ratings 1 parameter value logic supply voltage, v dd 2 7.5v driver supply voltage, v bb 2 90v output voltage 2 90v input voltage 2 -0.3v to v dd + 0.3v continuous total power dissipation at 25 o c free-air temperature: 3 20-lead plcc 3 20-lead sow 3 1500mw1500mw operating temperature range -45c +85c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the speciications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. all voltages are referenced to gnd. notes: 1. over operating free-air temperature 2. all voltages are referenced to v ss 3. for operation above 25 o c ambient derate linearly to 85 o c at 15mw/ o c pin conigurationproduct marking 1 20 20 1 2 yy = year sealed ww = week sealed a = assembler id l = lot number c = country of origin* = ?green? packaging * may be part of top marking top marking bottom marking yyww aaa hv6810wg llllllllll ccccccccccc 20-lead plcc 20-lead sow yy = year sealed ww = week sealed l = lot number a = assembler id c = country of origin* = ?green? packaging *may be part of top marking top marking bottom marking yyww aaa hv6810pj llllllllll ccccccccccc 20-lead sow (top view) 20-lead plcc (top view) package may or may not include the following marks: si or package may or may not include the following marks: si or part number package options packing hv6810pj-g 20-lead plcc* 48/tube hv6810pj-g m910 20-lead plcc* 1000/reel HV6810WG-G 20-lead sow 1000/reel ordering information-g denotes a lead (pb)-free / rohs compliant package * obsolescence notice issued for the product in the 20-lead plcc package. typical thermal resistance package ja 20-lead plcc 66 o c/w 20-lead sow 66 o c/w downloaded from: http:///
3 hv6810 supertex inc. www.supertex.com doc.# dsfp-hv6810 e070913 sym parameter min typ max units conditions t w(ckh) pulse duration, clock high 100 - - ns --- t w(leh) pulse duration, latch enable high 100 - - ns --- t su(d) setup time, data before clock 50 - - ns --- t h(d) hold time, data after clock 50 - - ns --- t ckh-leh delay time, clock to latch enable high 50 - - ns --- t pd * propagation delay time, latch enable to output - 300 - ns --- * switching characteristics, v bb = 60v, t a = 25 o c ac electrical characteristics (timing requirements over recommended operating conditions) dc electrical characteristics(v dd = 5.0v, v bb = 60v, v ss = 0v, t a = 25 o c unless otherwise noted) sym parameter min typ max units conditions v oh high level output voltage q outputs 57.5 58 - v i o = +25ma serial output 4.0 4.5 - v dd = +4.5v, i ol = +100a v ol low level output voltage q outputs - 0.15 1.0 v i o = -100a, blanking input at v dd serial output - 0.05 0.1 v dd = +4.5v, i o = -100a i ol low level q output current (pull-down current) 60 80 - a t a = max, v ol = +0.7v i o(off) off-state output current - -1.0 -15 a v o = 0v, blanking input at v dd i ih high level input current - 1.0 a v ln = v dd i dd supply current from v dd (standby) - 10 50 a all inputs at 0v, one q output high - 10 50 all inputs at 0v, all q outputs low i bb supply current from v bb - 0.05 0.1 ma all outputs low, all q outputs open - 0.05 0.1 all outputs high, all q outputs open * all typical values are at t a = 25 o c except for i ol and i o(off) . power-up sequence should be the following: 1. connect ground v ss 2. apply v dd 3. set all inputs (data, clk, enable, etc.) to a known state 4. apply v bb the v bb should not drop below v dd or loat during operation . power-down sequence should be the reverse of the above. downloaded from: http:///
4 hv6810 supertex inc. www.supertex.com doc.# dsfp-hv6810 e070913 timing diagram vali di rrelevant invalid valid previously stored data new data valid valid clock data in sr contents latch enable latch contents blanking q outputs switching waveforms t w(ckh) 50% 50% v ih v il v ih v il valid 50% 50% data clock t h(d) t su(d) 50% 50% 50% t ckh-leh valid valid 90% clock input latch enable q output t pd t w(leh) input timing v ih v il v ih v il v oh v ol output switching timing downloaded from: http:///
5 hv6810 supertex inc. www.supertex.com doc.# dsfp-hv6810 e070913 input and output equivalent circuits vdd data input vss input equivalent circuit vdd gnd da ta out vss q logic data output vbb high voltage output function table serial data input clock input shift register contents i 1 i 2 i 3 ... i n-1 i n serial data output le strobe input latch contents i 1 i 2 i 3 ... i n-1 i n blanking input output contents i 1 i 2 i 3 ... i n-1 i n h h r 1 r 2 ... r n-2 r n-1 r n-1 --- --- --- --- l l r 1 r 2 ... r n-2 r n-1 r n-1 x r 1 r 2 r 3 ... r n-1 r n r n --- --- x x x ... x x x l r 1 r 2 r 3 ... r n-1 r n p 1 p 2 p 3 ... p n-1 p n p n h p 1 p 2 p 3 ... p n-1 p n l p 1 p 2 p 3 ... p n-1 p n --- --- --- x x x ... x x h l l l ... l l notes: l = low logic level, h = high logic level, x = dont care, p = present state, r = previous state = low to high transition = high to low transition downloaded from: http:///
6 hv6810 supertex inc. www.supertex.com doc.# dsfp-hv6810 e070913 pin description 20-lead plcc (pj) pin # function description 1 q8 high voltage output. 2 q7 3 q6 4 clock input data is shifted into the data shift register on the positive edge of the clock. 5 n/c no connection. 6 vss usually v ss = 0v, ground connection. 7 vdd low voltage power supply. 8 le (strobe) when le is high, the shift register output is latched to q output. when le stays high, the latches are in transparent mode. 9 q5 high voltage output. 10 q4 11 q3 12 q2 13 q1 14 blanking when blanking is high, all qs are forced to a low state, regardless of data in each channel. 15 data in input data for the input shift register. 16 n/c no connection. 17 vbb high voltage power supply. 18 serial data out output data from the shift register. 19 q10 high voltage output. 20 q9 downloaded from: http:///
7 hv6810 supertex inc. www.supertex.com doc.# dsfp-hv6810 e070913 20-lead sow (wg) pin # function description 1 q8 high voltage output. 2 q7 3 q6 4 clock input data are shifted into the data shift register on the positive edge of the clock. 5 vss usually v ss = 0v, ground connection. 6 n/c no connection. 7 vdd low voltage power supply. 8 le (strobe) when le is high, the shift register output is latched to q output. when le stays high, the latches are in transparent mode. 9 q5 high voltage output. 10 q4 11 q3 12 q2 13 q1 14 blanking when blanking is high, all qs are forced to a low state, regardless of data in each channel. 15 data in input data for the input shift register. 16 vbb high voltage power supply. 17 serial data out output data from the shift register. 18 n/c no connection. 19 q10 high voltage output. 20 q9 pin description downloaded from: http:///
8 hv6810 supertex inc. www.supertex.com doc.# dsfp-hv6810 e070913 20-lead plcc package outline (pj) .353x.353in body, .180in height (max), .050in pitch symbol a a1 a2 b b1 d d1 e e1 e r dimension (inches) min .165 .090 .062 .013 .026 .385 .350 .385 .350 .050 bsc .025 nom .172 .105 - - - .390 .353 .390 .353 .035 max .180 .120 .083 .021 .032 .395 .356 .395 .356 .045 jedec registration ms-018, variation aa, issue a, june, 1993. drawings not to scale. supertex doc. #: dspd-20plccpj, version c031111 .150max .048/.042 x 45 o 1 .075max 3 8 13 18 d d1 e1 e top vi ew view b a a2 a1 seating plane note 1 (index area) .056/.042 x 45 o base plane .020min b vi ew b b1 20 horizontal side view vertical side vi ew note 2 .020max(3 places) r e notes: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. actual shape of this feature may vary. downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc . does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 9 hv6810 (the package drawings in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv6810 e070913 20-lead sow (wide body) package outline (wg) 12.80x7.50mm body, 2.65mm height (max), 1.27mm pitch symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 2.15* 0.10 2.05 0.31 12.60* 9.97* 7.40* 1.27 bsc 0.25 0.40 1.40 ref 0.25 bsc 0 o 5 o nom - - - - 12.80 10.30 7.50 - - - - max 2.65 0.30 2.55* 0.51 13.00* 10.63* 7.60* 0.75 1.27 8 o 15 o jedec registration ms-013, variation ac, issue e, sep. 2005. * this dimension is not speciied in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-20sowwg, version d041309. 1 20 e e1 d e b a a2 a1 seating plane a a top vi ew side view note 1 (index area 0.25d x 0.75e1) vi ew b vi ew a-a seating plane gauge plane l l1 l2 view b 1 h h note 1 note: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. downloaded from: http:///
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